-- 这是一个单行注释
/*
这是一个多行注释，
但请注意，标准VHDL不支持此种注释方式，
使用时需要确保工具链兼容。
*/

// 这是一个单行注释
/*
这是一个多行注释
可以跨越多行
*/

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Counter is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           count : out  STD_LOGIC_VECTOR(7 downto 0));
end Counter;

module Counter(
    input clk,
    input reset,
    output [7:0] count
);

module Counter(
    input wire clk,
    input wire reset,
    output reg [7:0] count
);

process(clk)
begin
    if rising_edge(clk) then
        if reset = '1' then
            count <= (others => '0');
        else
            count <= count + 1;
        end if;
    end if;
end process;

always @(posedge clk) begin
    if (reset) 
        count <= 0;
    else 
        count <= count + 1;
end

signal my_vector : STD_LOGIC_VECTOR(7 downto 0);
my_vector <= "00001111";

reg [7:0] my_vector;
my_vector = 8'b00001111;

process(all)
begin
    if (a = '1' and b = '0') then
        result <= '1';
    else
        result <= '0';
    end if;
end process;

always @(*)
begin
    if (a == 1'b1 && b == 1'b0)
        result = 1'b1;
    else
        result = 1'b0;
end

process
begin
    for i in 0 to 7 loop
        my_array(i) <= i;
    end loop;
    wait;
end process;

integer i;
always @(*)
begin
    for (i = 0; i <= 7; i = i + 1)
        my_array[i] = i;
end

function add_two_numbers(a, b: integer) return integer is
begin
    return a + b;
end function;

-- 使用
signal result: integer;
result <= add_two_numbers(5, 3);

function integer add_two_numbers;
    input integer a, b;
begin
    add_two_numbers = a + b;
end
endfunction

// 使用
reg [31:0] result;
always @(*)
    result = add_two_numbers(5, 3);

entity Adder is
    Port ( A : in  INTEGER;
           B : in  INTEGER;
           Sum : out INTEGER);
end Adder;

architecture Behavioral of Adder is
begin
    Sum <= A + B;
end Behavioral;

-- 实例化
signal a, b, sum : INTEGER;
begin
    u_adder: entity work.Adder
        port map (A => a, B => b, Sum => sum);

module Adder(
    input integer A,
    input integer B,
    output integer Sum
);
    assign Sum = A + B;
endmodule

// 实例化
integer a, b, sum;
Adder u_adder (
    .A(a),
    .B(b),
    .Sum(sum)
);

process(clk)
begin
    if rising_edge(clk) then
        if en = '1' then
            reg <= data_in;
        end if;
    end if;
end process;

always @(posedge clk) begin
    if (en)
        reg <= data_in;
end

type my_array_type is array (0 to 7) of INTEGER;
signal my_array : my_array_type;
begin
    my_array(0) <= 10;
    -- 其他元素初始化

reg [31:0] my_array [0:7];
initial begin
    my_array[0] = 10;
    // 其他元素初始化
end

process(a, b, c)
begin
    y <= (a and b) or c;
end process;

assign y = (a & b) | c;

always @* begin
     y = (a & b) | c;
end

entity GenericAdder is
    generic ( WIDTH : integer := 8 );
    port ( A : in  std_logic_vector(WIDTH-1 downto 0);
           B : in  std_logic_vector(WIDTH-1 downto 0);
           Sum : out std_logic_vector(WIDTH-1 downto 0) );
end GenericAdder;

architecture Behavioral of GenericAdder is
begin
    Sum <= A + B;
end Behavioral;

module GenericAdder #(parameter WIDTH = 8) (
    input [WIDTH-1:0] A,
    input [WIDTH-1:0] B,
    output [WIDTH-1:0] Sum
);
    assign Sum = A + B;
endmodule

type state_type is (IDLE, WORKING, DONE);
signal current_state, next_state: state_type;

process(clk)
begin
    if rising_edge(clk) then
        current_state <= next_state;
    end if;
end process;

process(current_state, input_signal)
begin
    case current_state is
        when IDLE =>
            if input_signal = '1' then
                next_state <= WORKING;
            else
                next_state <= IDLE;
            end if;
        when WORKING =>
            next_state <= DONE;
        when DONE =>
            next_state <= IDLE;
        when others =>
            next_state <= IDLE;
    end case;
end process;

typedef enum {IDLE, WORKING, DONE} state_type;
reg [1:0] current_state, next_state;

always @(posedge clk) begin
    current_state <= next_state;
end

always @(*) begin
    case (current_state)
        IDLE: begin
            if (input_signal)
                next_state = WORKING;
            else
                next_state = IDLE;
        end
        WORKING: begin
            next_state = DONE;
        end
        DONE: begin
            next_state = IDLE;
        end
        default: begin
            next_state = IDLE;
        end
    endcase
end

type reg_array is array (0 to 7) of std_logic_vector(7 downto 0);
signal registers: reg_array;

reg [7:0] registers [0:7];

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DFF is
    Port ( D : in STD_LOGIC;
           CLK : in STD_LOGIC;
           Q : out STD_LOGIC);
end DFF;

architecture Behavioral of DFF is
begin
    process(CLK)
    begin
        if rising_edge(CLK) then
            Q <= D;
        end if;
    end process;
end Behavioral;

module DFF(
    input D,
    input CLK,
    output reg Q
);
    always @(posedge CLK) begin
        Q <= D;
    end
endmodule